`include "define.v"

module openmips (
    input wire clk,
    input wire rst,
    
    input wire[5:0]                int_i,
    input wire[`RegBus] rom_data_i,
    output wire[`RegBus] rom_addr_o,
    output wire rom_ce_o,
    input wire[`RegBus]           ram_data_i,
	output wire[`RegBus]           ram_addr_o,
	output wire[`RegBus]           ram_data_o,
	output wire                    ram_we_o,
	output wire[3:0]               ram_sel_o,
	output wire                     ram_ce_o,
    output wire                    timer_int_o
);
    //pc -> if_id
    wire[`InstAddrBus] if_pc;

    //if_id -> id
    wire[`InstAddrBus] pc_i;
    wire[`InstBus] inst_i;

    //id -> id_ex
    wire[`AluOpBus] id_aluop;
    wire[`AluSelBus] id_alusel;
    wire[`RegBus] id_reg1;
    wire[`RegBus] id_reg2;
    wire[`RegAddrBus] id_wd;
    wire id_wreg;
    wire[`RegBus] bus_inst_id2idex;

    //id_ex -> ex
    wire[`AluOpBus] aluop_i;
    wire[`AluSelBus] alusel_i;
    wire[`RegBus] reg1_data_i;
    wire[`RegBus] reg2_data_i;
    wire[`RegAddrBus] write_reg_addr_i;
    wire write_reg_enable_i;
    wire[`RegBus] bus_inst_idex2ex;

    //ex -> ex_mem
    wire[`RegBus] ex_wdata;
    wire[`RegAddrBus] ex_wd;
    wire ex_wreg;
    wire[`RegBus] bus_ex2exmem_hi;
    wire[`RegBus] bus_ex2exmem_lo;
    wire bus_ex2exmem_whilo;

    wire[`DoubleRegBus] bus_ex2exmem_hilo;
    wire[1:0] bus_ex2exmem_cnt;

    wire[`DoubleRegBus] bus_exmem2ex_hilo;
    wire[1:0] bus_exmem2ex_cnt;

    //数据相关 ex->id
    wire bus_ex2id_write_reg_enable;
    wire[`RegAddrBus] bus_ex2id_write_reg_addr;
    wire[`RegBus] bus_ex2id_write_data;

    //处理数据相关
    wire[`RegBus] bus_mem2ex_hi;
    wire[`RegBus] bus_mem2ex_lo;
    wire bus_mem2ex_whilo;

    wire[`RegBus] bus_wb2ex_hi;
    wire[`RegBus] bus_wb2ex_lo;
    wire bus_wb2ex_whilo;

    //ex_mem -> mem
    wire[`RegBus] wdata_i;
    wire[`RegAddrBus] wd_i;
    wire wreg_i;
    wire[`RegBus] bus_exmem2mem_hi;
    wire[`RegBus] bus_exmem2mem_lo;
    wire bus_exmem2mem_whilo;

    //mem -> mem_wb
    wire[`RegBus] mem_wdata;
    wire[`RegAddrBus] mem_wd;
    wire mem_wreg;
    wire[`RegBus] bus_mem2memwb_hi;
    wire[`RegBus] bus_mem2memwb_lo;
    wire bus_mem2memwb_whilo;

    //数据相关 mem->id
    wire bus_mem2id_write_reg_enable;
    wire[`RegAddrBus] bus_mem2id_write_reg_addr;
    wire[`RegBus] bus_mem2id_write_data;

    //wb->hilo
    wire bus_wb2hilo_we;
    wire[`RegBus] bus_wb2hilo_hi;
    wire[`RegBus] bus_wb2hilo_lo;

    //mem_wb -> regfile
    wire write_enable;
    wire[`RegAddrBus] reg_write_addr;
    wire[`RegBus] reg_write_data;

    //regfile -> id
    wire[`RegBus] id_reg1_data_i;
    wire[`RegBus] id_reg2_data_i;

    //id -> regfile
    wire[`RegAddrBus] raddr1;
    wire raddr1_enable;
    wire[`RegAddrBus] raddr2;
    wire raddr2_enable;

    //hilo -> ex
    wire[`RegBus] bus_hilo2ex_hi;
    wire[`RegBus] bus_hilo2ex_lo;

    //stall
    wire[`StallBus] bus_stall;
    wire bus_stall_id2ctrl;
    wire bus_stall_ex2ctrl;

    //ex -> div
    wire bus_signed_div_ex2div;
    wire[31:0] bus_opdata1_ex2div;
    wire[31:0] bus_opdata2_ex2div;
    wire bus_start_ex2div;
    wire bus_annul_ex2div;

    wire[63:0] bus_result_div2ex;
    wire bus_ready_div2ex;

    //id->pc
    wire[`RegBus] bus_branch_addr_id2pc;
    wire bus_branch_flag_id2pc;

    wire bus_is_in_delayslot_id2idex;
    wire[`RegBus] bus_link_addr_id2idex;
    wire bus_next_inst_in_delay_id2idex;

    wire[`RegBus] bus_link_addr_idex2ex;
    wire bus_is_in_delay_idex2ex;
    wire bus_is_in_delay_idex2id;

    wire[`AluOpBus] bus_aluop_ex2exmem;
    wire[`RegBus] bus_mem_addr_ex2exmem;
    wire[`RegBus] bus_reg2_ex2exmem;

    wire[`AluOpBus] bus_aluop_exmem2mem;
    wire[`RegBus] bus_mem_addr_exmem2mem;
    wire[`RegBus] bus_reg2_exmem2mem;

    wire bus_LLbit_LLbit2mem;
    wire bus_LLbit_we_mem2memwb;
    wire bus_LLbit_value_mem2memwb;

    wire bus_wb_LLbit_we_memwb2LLbit;
    wire bus_wb_LLbit_value_memwb2LLbit;

    //cp0 bus
    wire[`RegBus] bus_cp0_reg_data_ex2exmem;
    wire[4:0] bus_cp0_reg_write_addr_ex2exmem;
    wire bus_cp0_reg_we_ex2exmem;

    wire[`RegBus] bus_cp0_reg_data_exmem2mem;
    wire[4:0] bus_cp0_reg_write_addr_exmem2mem;
    wire bus_cp0_reg_we_exmem2mem;

    wire[`RegBus] bus_cp0_reg_data_mem2memwb;
    wire[4:0] bus_cp0_reg_write_addr_mem2memwb;
    wire bus_cp0_reg_we_mem2memwb;

    wire[`RegBus] bus_cp0_reg_data_memwb2cp0;
    wire[4:0] bus_cp0_reg_write_addr_memwb2cp0;
    wire bus_cp0_reg_we_memwb2cp0;

    wire[4:0] bus_cp0_reg_read_addr_ex2cp0;
    wire[`RegBus] bus_cp0_reg_data_cp02ex;

    wire bus_flush;
    wire[31:0] bus_excepttype_id2idex;
    wire[`RegBus] bus_current_inst_address_id2idex;

    wire[31:0] bus_excepttype_idex2ex;
    wire[`RegBus] bus_current_inst_address_idex2ex;

    wire[31:0] bus_exceptype_ex2exmem;
    wire[`RegBus] bus_current_inst_address_ex2exmem;
    wire bus_is_in_delay_ex2exmem;

    wire[31:0] bus_exceptype_exmem2mem;
    wire[`RegBus] bus_current_inst_address_exmem2mem;
    wire bus_is_in_delay_exmem2mem;

    wire[31:0] bus_exceptype_mem2cp0;
    wire[`RegBus] bus_current_inst_address_mem2cp0;
    wire bus_is_in_delay_mem2cp0;

    wire[`RegBus] bus_cp0_epc_mem2ctrl;

    wire[`RegBus] bus_new_pc_ctrl2pc;

    wire[`RegBus]   bus_cp0_count;
	wire[`RegBus]	bus_cp0_compare;
	wire[`RegBus]	bus_cp0_config;
	wire[`RegBus]	bus_cp0_prid;
    wire[`RegBus]	bus_cp0_status_cp02mem;
	wire[`RegBus]	bus_cp0_cause_cp02mem;
	wire[`RegBus]	bus_cp0_epc_cp02mem;

    assign rom_addr_o = if_pc;

    //PC实例
    pc_reg pc_reg0(
        .clk(clk),
        .rst(rst),
        .pc(if_pc),
        .flush(bus_flush),
        .new_pc(bus_new_pc_ctrl2pc),
        .ce(rom_ce_o),
        .stall(bus_stall),
        .branch_flag_i(bus_branch_flag_id2pc),
        .branch_addr_i(bus_branch_addr_id2pc)
    );

    //if_id 实例
    if_id if_id0(
        .if_pc(if_pc),
        .if_inst(rom_data_i),
        .rst(rst),
        .clk(clk),
        .id_pc(pc_i),
        .id_inst(inst_i),
        .flush(bus_flush),
        .if_stall(bus_stall)
    );
    //id实例
    id id0(
        .rst(rst),
        .pc_i(pc_i),
        .inst_i(inst_i),
        .reg1_data_i(id_reg1_data_i),
        .reg2_data_i(id_reg2_data_i),
        .is_in_delayslot_i(bus_is_in_delay_idex2id),
        .ex_aluop_i(aluop_i),

        .aluop_o(id_aluop),
        .alusel_o(id_alusel),
        .reg1_data_o(id_reg1),
        .reg2_data_o(id_reg2),
        .write_reg_addr_o(id_wd),
        .write_reg_enable(id_wreg),

        .reg2_addr_o(raddr2),
        .reg2_read_enable_o(raddr2_enable),
        .reg1_addr_o(raddr1),
        .reg1_read_enable_o(raddr1_enable),

        .ex_write_reg_enable_i(ex_wreg),
        .ex_write_reg_addr_i(ex_wd),
        .ex_write_data_i(ex_wdata),

        .mem_write_reg_enable_i(mem_wreg),
        .mem_write_reg_addr_i(mem_wd),
        .mem_write_data_i(mem_wdata),
        .stallreq(bus_stall_id2ctrl),
        .next_inst_in_delayslot_o(bus_next_inst_in_delay_id2idex),
	
        .branch_flag_o(bus_branch_flag_id2pc),
        .branch_target_address_o(bus_branch_addr_id2pc),       
        .link_addr_o(bus_link_addr_id2idex),
        .is_in_delayslot_o(bus_is_in_delayslot_id2idex),
        .excepttype_o(bus_excepttype_id2idex),
        .current_inst_address_o(bus_current_inst_address_id2idex),
        .inst_o(bus_inst_id2idex)
    );


    //regfile模块
    regfile regfile0(
        .rst(rst),
        .clk(clk),

        .reg_write_addr(reg_write_addr),
        .reg_write_data(reg_write_data),
        .write_enable(write_enable),

        .raddr1(raddr1),
        .raddr1_enable(raddr1_enable),
        .reg_read_data1(id_reg1_data_i),

        .raddr2(raddr2),
        .raddr2_enable(raddr2_enable),
        .reg_read_data2(id_reg2_data_i)
    );

    //id_ex模块
    id_ex id_ex0(
        .rst(rst),
        .clk(clk),
        .id_aluop(id_aluop),
        .id_alusel(id_alusel),
        .id_reg1(id_reg1),
        .id_reg2(id_reg2),
        .id_wd(id_wd),
        .id_wreg(id_wreg),
        .id_link_address(bus_link_addr_id2idex),
	    .id_is_in_delayslot(bus_is_in_delayslot_id2idex),
	    .next_inst_in_delayslot_i(bus_next_inst_in_delay_id2idex),
        .id_excepttype(bus_excepttype_id2idex),
        .id_current_inst_address(bus_current_inst_address_id2idex),

        .ex_aluop(aluop_i),
        .ex_alusel(alusel_i),
        .ex_reg1(reg1_data_i),
        .ex_reg2(reg2_data_i),
        .ex_wd(write_reg_addr_i),
        .ex_wreg(write_reg_enable_i),
        .if_stall(bus_stall),
        .flush(bus_flush),
        .ex_link_address(bus_link_addr_idex2ex),
        .ex_is_in_delayslot(bus_is_in_delay_idex2ex),
        .is_in_delayslot_o(bus_is_in_delay_idex2id),
        .id_inst(bus_inst_id2idex),
        .ex_inst(bus_inst_idex2ex),
        .ex_excepttype(bus_excepttype_idex2ex),
        .ex_current_inst_address(bus_current_inst_address_idex2ex)
    );
    //ex模块
    ex ex0(
        .rst(rst),
        .aluop_i(aluop_i),
        .alusel_i(alusel_i),
        .reg1_data_i(reg1_data_i),
        .reg2_data_i(reg2_data_i),
        .write_reg_addr_i(write_reg_addr_i),
        .write_reg_enable_i(write_reg_enable_i),
        .link_address_i(bus_link_addr_idex2ex),
	    .is_in_delayslot_i(bus_is_in_delay_idex2ex),

        .hi_i(bus_hilo2ex_hi),
        .lo_i(bus_hilo2ex_lo),
        .hilo_temp_i(bus_exmem2ex_hilo),
        .cnt_i(bus_exmem2ex_cnt),
        .div_result_i(bus_result_div2ex),
		.div_ready_i(bus_ready_div2ex), 

        //数据相关处理
        .mem_hi_i(bus_mem2memwb_hi),
        .mem_lo_i(bus_mem2memwb_lo),
        .mem_hilo_write_enable_i(bus_mem2memwb_whilo),
        .wb_hi_i(bus_wb2hilo_hi),
        .wb_lo_i(bus_wb2hilo_lo),
        .wb_hilo_write_enable_i(bus_wb2hilo_we),
        .inst_i(bus_inst_idex2ex),
        .excepttype_i(bus_excepttype_idex2ex),
        .current_inst_address_i(bus_current_inst_address_idex2ex),

        .mem_cp0_reg_we(bus_cp0_reg_we_mem2memwb),
        .mem_cp0_reg_write_addr(bus_cp0_reg_write_addr_mem2memwb),
        .mem_cp0_reg_data(bus_cp0_reg_data_mem2memwb),

        .wb_cp0_reg_we(bus_cp0_reg_we_memwb2cp0),
        .wb_cp0_reg_write_addr(bus_cp0_reg_write_addr_memwb2cp0),
        .wb_cp0_reg_data(bus_cp0_reg_data_memwb2cp0),

        .cp0_reg_data_i(bus_cp0_reg_data_cp02ex),
        .cp0_reg_read_addr_o(bus_cp0_reg_read_addr_ex2cp0),

        .cp0_reg_we_o(bus_cp0_reg_we_ex2exmem),
        .cp0_reg_write_addr_o(bus_cp0_reg_write_addr_ex2exmem),
        .cp0_reg_data_o(bus_cp0_reg_data_ex2exmem),

        .write_reg_data_o(ex_wdata),
        .write_reg_addr_o(ex_wd),
        .write_reg_enable_o(ex_wreg),
        
        .hi_o(bus_ex2exmem_hi),
        .lo_o(bus_ex2exmem_lo),
        .whilo_o(bus_ex2exmem_whilo),

        .hilo_temp_o(bus_ex2exmem_hilo),
        .cnt_o(bus_ex2exmem_cnt),
        .stallreq(bus_stall_ex2ctrl),
        .div_opdata1_o(bus_opdata1_ex2div),
	    .div_opdata2_o(bus_opdata2_ex2div),
	    .div_start_o(bus_start_ex2div),
	    .signed_div_o(bus_signed_div_ex2div),
        .aluop_o(bus_aluop_ex2exmem),
        .mem_addr_o(bus_mem_addr_ex2exmem),
        .reg2_data_o(bus_reg2_ex2exmem),
        .is_in_delayslot_o(bus_is_in_delay_ex2exmem),
        .excepttype_o(bus_exceptype_ex2exmem),
        .current_inst_address_o(bus_current_inst_address_ex2exmem)
    );

    //ex_mem模块
    ex_mem ex_mem0(
        .rst(rst),
        .clk(clk),
        .ex_wdata(ex_wdata),
        .ex_wd(ex_wd),
        .ex_wreg(ex_wreg),

        .ex_hilo_write_enable_i(bus_ex2exmem_whilo),
        .ex_hi(bus_ex2exmem_hi),
        .ex_lo(bus_ex2exmem_lo),
        .ex_aluop(bus_aluop_ex2exmem),
        .ex_mem_addr(bus_mem_addr_ex2exmem),
        .ex_reg2(bus_reg2_ex2exmem),

        .ex_cp0_reg_we(bus_cp0_reg_we_ex2exmem),
        .ex_cp0_reg_write_addr(bus_cp0_reg_write_addr_ex2exmem),
        .ex_cp0_reg_data(bus_cp0_reg_data_ex2exmem),
        .ex_excepttype(bus_exceptype_ex2exmem),
        .ex_is_in_delayslot(bus_is_in_delay_ex2exmem),
        .ex_current_inst_address(bus_current_inst_address_ex2exmem),

        .mem_hilo_write_enable_o(bus_exmem2mem_whilo),
        .mem_hi(bus_exmem2mem_hi),
        .mem_lo(bus_exmem2mem_lo),

        .mem_wdata(wdata_i),
        .mem_wd(wd_i),
        .mem_wreg(wreg_i),
        .flush(bus_flush),
        .hilo_i(bus_ex2exmem_hilo),
        .cnt_i(bus_ex2exmem_cnt),
        .if_stall(bus_stall),
        .cnt_o(bus_exmem2ex_cnt),
        .hilo_o(bus_exmem2ex_hilo),

        .mem_cp0_reg_we(bus_cp0_reg_we_exmem2mem),
        .mem_cp0_reg_write_addr(bus_cp0_reg_write_addr_exmem2mem),
        .mem_cp0_reg_data(bus_cp0_reg_data_exmem2mem),

        .mem_aluop(bus_aluop_exmem2mem),
        .mem_mem_addr(bus_mem_addr_exmem2mem),
        .mem_reg2(bus_reg2_exmem2mem),
        .mem_excepttype(bus_exceptype_exmem2mem),
        .mem_is_in_delayslot(bus_is_in_delay_exmem2mem),
        .mem_current_inst_address(bus_current_inst_address_exmem2mem)
    );

    //mem模块
    mem mem0(
        .rst(rst),
        .wdata_i(wdata_i),
        .wd_i(wd_i),
        .wreg_i(wreg_i),
        .hi_i(bus_exmem2mem_hi),
        .lo_i(bus_exmem2mem_lo),
        .whilo_i(bus_exmem2mem_whilo),

        .aluop_i(bus_aluop_exmem2mem),
        .mem_addr_i(bus_mem_addr_exmem2mem),
        .reg2_i(bus_reg2_exmem2mem),
        .mem_data_i(ram_data_i),

        .cp0_reg_we_i(bus_cp0_reg_we_exmem2mem),
	    .cp0_reg_write_addr_i(bus_cp0_reg_write_addr_exmem2mem),
	    .cp0_reg_data_i(bus_cp0_reg_data_exmem2mem),

        .excepttype_i(bus_exceptype_exmem2mem),
	    .is_in_delayslot_i(bus_is_in_delay_exmem2mem),
	    .current_inst_address_i(bus_current_inst_address_exmem2mem),
        .wb_cp0_reg_we(bus_cp0_reg_we_memwb2cp0),
	    .wb_cp0_reg_write_addr(bus_cp0_reg_write_addr_memwb2cp0),
	    .wb_cp0_reg_data(bus_cp0_reg_data_memwb2cp0),
        .cp0_status_i(bus_cp0_status_cp02mem),
	    .cp0_cause_i(bus_cp0_cause_cp02mem),
	    .cp0_epc_i(bus_cp0_epc_cp02mem),

        .wdata_o(mem_wdata),
        .wd_o(mem_wd),
        .wreg_o(mem_wreg),

        .hi_o(bus_mem2memwb_hi),
        .lo_o(bus_mem2memwb_lo),
        .whilo_o(bus_mem2memwb_whilo),

        .cp0_reg_we_o(bus_cp0_reg_we_mem2memwb),
        .cp0_reg_write_addr_o(bus_cp0_reg_write_addr_mem2memwb),
        .cp0_reg_data_o(bus_cp0_reg_data_mem2memwb),

        .mem_addr_o(ram_addr_o),
		.mem_we_o(ram_we_o),
		.mem_sel_o(ram_sel_o),
		.mem_data_o(ram_data_o),
		.mem_ce_o(ram_ce_o),
        .LLbit_i(bus_LLbit_LLbit2mem),
        .wb_LLbit_we_i(bus_wb_LLbit_we_memwb2LLbit),
        .wb_LLbit_value_i(bus_wb_LLbit_value_memwb2LLbit),
        .LLbit_we_o(bus_LLbit_we_mem2memwb),
        .LLbit_value_o(bus_LLbit_value_mem2memwb),
        .excepttype_o(bus_exceptype_mem2cp0),
        .cp0_epc_o(bus_cp0_epc_mem2ctrl),
        .current_inst_address_o(bus_current_inst_address_mem2cp0),
        .is_in_delayslot_o(bus_is_in_delay_mem2cp0)
    );

    mem_wb mem_wb0(
        .rst(rst),
        .clk(clk),
        .mem_wdata(mem_wdata),
        .mem_wd(mem_wd),
        .mem_wreg(mem_wreg),
        .mem_whilo(bus_mem2memwb_whilo),
        .mem_hi(bus_mem2memwb_hi),
        .mem_lo(bus_mem2memwb_lo),
        .flush(bus_flush),

        .mem_cp0_reg_we(bus_cp0_reg_we_mem2memwb),
        .mem_cp0_reg_write_addr(bus_cp0_reg_write_addr_mem2memwb),
        .mem_cp0_reg_data(bus_cp0_reg_data_mem2memwb),

        .wb_wdata(reg_write_data),
        .wb_wd(reg_write_addr),
        .wb_wreg(write_enable),
        .wb_whilo(bus_wb2hilo_we),
        .wb_hi(bus_wb2hilo_hi),
        .wb_lo(bus_wb2hilo_lo),
        .if_stall(bus_stall),
        .mem_LLbit_we(bus_LLbit_we_mem2memwb),
        .mem_LLbit_value(bus_LLbit_value_mem2memwb),
        .wb_LLbit_we(bus_wb_LLbit_we_memwb2LLbit),
        .wb_LLbit_value(bus_wb_LLbit_value_memwb2LLbit),
        .wb_cp0_reg_we(bus_cp0_reg_we_memwb2cp0),
        .wb_cp0_reg_write_addr(bus_cp0_reg_write_addr_memwb2cp0),
        .wb_cp0_reg_data(bus_cp0_reg_data_memwb2cp0)
    );

    hilo_reg hilo_reg0(
        .clk(clk),
        .rst(rst),
        .we(bus_wb2hilo_we),
        .hi_in(bus_wb2hilo_hi),
        .lo_in(bus_wb2hilo_lo),
        .hi_out(bus_hilo2ex_hi),
        .lo_out(bus_hilo2ex_lo)
    );

    ctrl ctrl0(
        .rst(rst),
        .stallreq_from_id(bus_stall_id2ctrl),
        .stallreq_from_ex(bus_stall_ex2ctrl),
        .stall(bus_stall),
        .excepttype_i(bus_exceptype_mem2cp0),
        .cp0_epc_i(bus_cp0_epc_mem2ctrl),
        .new_pc(bus_new_pc_ctrl2pc),
        .flush(bus_flush)
    );

    div div0(
		.clk(clk),
		.rst(rst),

		.signed_div_i(bus_signed_div_ex2div),
		.opdata1_i(bus_opdata1_ex2div),
		.opdata2_i(bus_opdata2_ex2div),
		.start_i(bus_start_ex2div),
		.annul_i(1'b0),
	
		.result_o(bus_result_div2ex),
		.ready_o(bus_ready_div2ex)
	);

    LLbit_reg LLbit0(
        .we(bus_wb_LLbit_we_memwb2LLbit),
        .LLbit_i(bus_wb_LLbit_value_memwb2LLbit),
        .clk(clk),
        .flush(bus_flush),
        .rst(rst),
        .LLbit_o(bus_LLbit_LLbit2mem)
    );

    cp0_reg cp0_reg0(
        .clk(clk),
        .rst(rst),
        .we_i(bus_cp0_reg_we_memwb2cp0),
        .waddr_i(bus_cp0_reg_write_addr_memwb2cp0),
        .raddr_i(bus_cp0_reg_read_addr_ex2cp0),
        .data_i(bus_cp0_reg_data_memwb2cp0),
        .int_i(int_i),
        .data_o(bus_cp0_reg_data_cp02ex),
        .current_inst_addr_i(bus_current_inst_address_mem2cp0),
	    .is_in_delayslot_i(bus_is_in_delay_mem2cp0),
        .excepttype_i(bus_exceptype_mem2cp0),
        .count_o(bus_cp0_count),
        .compare_o(bus_cp0_compare),
        .status_o(bus_cp0_status_cp02mem),
        .cause_o(bus_cp0_cause_cp02mem),
        .epc_o(bus_cp0_epc_cp02mem),
        .config_o(bus_cp0_config),
        .prid_o(bus_cp0_prid),
        .timer_int_o(timer_int_o) 
    );

endmodule